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Cadence Announces Agilent Technologies' Successful Implementation of a 90nm Digital Signal Processor Using the Cadence Encounter Digital IC Platform
Cadence Encounter Facilitates the On-Time Tape-Out of 400MHz DSP
SAN JOSE, Calif.—(BUSINESS WIRE)—March 5, 2004—
Cadence Design Systems, Inc. (NYSE:CDN) today announced that
Agilent Technologies Inc. has successfully implemented a
two-million-plus-gate digital signal processor (DSP) in 90nm process
technology using the Cadence(R) Encounter(TM) digital IC
implementation platform. The new generation technology behind the
Cadence Encounter platform helped the Agilent team complete the
aggressive design schedule on time. The Cadence Encounter platform
again demonstrates that it provides a rapid route to complex,
high-performance system-on-chips (SoC).
"We are delighted with the results we achieved with the Cadence
Encounter platform. Implementing a 400MHz DSP in 90nm requires cutting
edge tools," said Jay McDougal, Microprocessor Design Methodology
Program Manager for Agilent's ASIC Products Division. "Encounter
physical implementation technology combined with great support by
Cadence helped us to successfully release this chip on schedule."
For the implementation of this DSP, Agilent used the Cadence SoC
Encounter(TM) physical implementation tool. A core technology of the
Cadence Encounter platform, the SoC Encounter tool offers a complete
digital IC implementation solution for nanometer designs including
NanoRoute(TM) Ultra for nanometer routing. The SoC Encounter tool
provides a fast route to quality silicon with proven tools and
methodologies for implementing exceedingly complex, high-performance
chips, like the Agilent DSP. The SoC Encounter tool replaces
traditional linear design flows with a new design strategy that
minimizes time to wires and full-chip iteration time. The SoC
Encounter physical implementation tool provides a higher level of
quality of silicon (QoS) by measuring a design's physical
characteristics, in terms of area, performance and power -- using
wires.
"We are pleased to see Agilent successfully implement a 90
nanometer DSP using the Cadence Encounter platform," said Wei-Jin Dai,
platform vice president, digital IC implementation, Cadence Design
Systems, Inc. "Once again, Encounter continues to achieve validation
in a leading edge production environment."
About Cadence
Cadence is the largest supplier of electronic design technologies,
methodology services, and design services. Cadence solutions are used
to accelerate and manage the design of semiconductors, computer
systems, networking and telecommunications equipment, consumer
electronics, and a variety of other electronics-based products. With
approximately 4,800 employees and 2003 revenues of approximately $1.1
billion, Cadence has sales offices, design centers, and research
facilities around the world. The company is headquartered in San Jose,
Calif., and traded on the New York Stock Exchange under the symbol
CDN. More information about the company, its products and services is
available at www.cadence.com.
Cadence and the Cadence logo are registered trademarks and
Encounter, SoC Encounter and NanoRoute are trademarks of Cadence
Design Systems, Inc. All other trademarks are the property of their
respective owners.
Contact:
The Hoffman Agency (for Cadence Design Systems)
Carolyn Robinson, 408-975-3065
crobinson@hoffman.com
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